
dsPIC30F3014
/4013
DS7
0138G
-page
158
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TABLE 20-7:
SYSTEM INTEGRATION REGISTER MAP(1)
TABLE 20-8:
DEVICE CONFIGURATION REGISTER MAP(1)
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
RCON
0740
TRAPR
IOPUWR
BGST
LVDEN
LVDL<3:0>
EXTR
SWR
SWDTEN WDTO
SLEEP
IDLE
BOR
POR
(Note 2)
OSCCON
0742
—
COSC<2:0>
—
NOSC<2:0>
POST<1:0>
LOCK
—CF
—
LPOSCEN OSWEN
(Note 3)
OSCTUN
0744
—
TUN3
TUN2
TUN1
TUN0
0000 0000 0000 0000
PMD1
0770
T5MD(4)
T4MD(4)
T3MD
T2MD
T1MD
—
DCIMD(4) I2CMD U2MD
U1MD
—SPI1MD
—
C1MD
ADCMD
0000 0000 0000 0000
PMD2
0772
IC8MD(4) IC7MD(4)
—
—IC2MD
IC1MD
—
—OC4MD(4) OC3MD(4)
OC2MD
OC1MD
0000 0000 0000 0000
Legend:
— = unimplemented bit, read as ‘0’
Note
1:
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2:
Reset state depends on type of Reset.
3:
Reset state depends on Configuration bits.
4:
These bits are not available in dsPIC30F3014 devices.
Name
Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FOSC
F80000
FCKSM<1:0>
—
—FOS<2:0>
—
FPR<4:0>
FWDT
F80002
FWDTEN
—
FWPSA<1:0>
FWPSB<3:0>
FBORPOR
F80004
MCLREN
—
PWMPIN(2)
HPOL(2)
LPOL(2)
BOREN
—BORV<1:0>
—
—FPWRT<1:0>
FBS
F80006
—
Reserved(3)
—
Reserved(3)
—
Reserved(3)
FSS
F80008
—
Reserved(3)
—
Reserved(3)
—
Reserved(3)
FGS
F8000A
—
Reserved(4)
GCP
GWRP
FICD
F8000C
BKBUG
COE
—
—ICS<1:0>
Legend:
— = unimplemented bit, read as ‘0’
Note
1:
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2:
These bits are reserved (read as ‘1’ and must be programmed as ‘1’).
3:
Reserved bits read as ‘1’ and must be programmed as ‘1’.
4:
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).